The present invention relates to a liquid crystal display device, and more particularly to a technique effectively applied to a video signal line driver circuit (drain driver) of a liquid crystal display device capable of carrying out multi-gray scale display.
A liquid crystal device of an active matrix type having an active element (for example, a thin film transistor) for each pixel and switching the active element is widely used as a display device of a notebook personal computer or the like.
In the active matrix type liquid crystal display device, a video signal voltage (a gray scale voltage in correspondence with display data; hereinafter referred to as a gray scale voltage) is applied to a pixel electrode via an active element and accordingly, there is produced no crosstalk among respective pixels, a special driving method need not be used for preventing crosstalk as in a simple matrix type liquid crystal display device and multi-gray scale display is feasible.
There has been known as one of the active matrix type liquid crystal display device, a liquid crystal display module of a TFT (Thin Film Transistor) type having a liquid crystal display panel of a TFT type (TFT-LCD), drain drivers arranged at the top side of the liquid crystal display panel and gate drivers and an interface circuit arranged at the side of the liquid crystal display panel.
In the liquid crystal display module of the TFT type, there are provided in the drain driver, a multi-gray scale voltage generating circuit, a gray scale voltage selector for selecting one gray scale voltage in correspondence with display data from among a plurality of gray scale voltages generated by the multi-gray scale voltage generating circuit and an amplifier circuit receiving the one gray scale voltage selected by the gray scale voltage selector.
In this case, the gray scale voltage selector is supplied with respective bit values of the display data via a level shift circuit.
Further, such a technique is described in, for example, Japanese Patent Laid-Open No. Hei 9-281930 (corresponding to U.S. application Ser. No. 08/826,973 filed on Apr. 9, 1997, now U.S. Pat. No. 5,995,073).
The concept of eliminating offset voltages in amplifiers is disclosed in the following patent applications or patents: Japanese Patent Laid-Open Nos. Sho 55-1702 (Application No. Sho 53-72691, laid open on Jan. 8, 1980); Sho 59-149408 (Application No. Sho 59-17278, laid open on Aug. 27, 1984); Hei 1-202909 (Application No. Sho 63-26572, laid open on Aug. 15, 1989); Hei 4-38004 (Application No. Hei 2-145827, laid open on Feb. 7, 1992); U.S. Pat. No. 4,902,981 (application Ser. No. 07/283,149, issued on Feb. 20, 1990); U.S. Pat. No. Re. 34,428 (application Ser. No. 07/846,442, reissued on Nov. 2, 1993); and U.S. Pat. No. 5,334,944 (application Ser. No. 08/168,399, issued on Aug. 2, 1994).
In recent years, in liquid crystal display devices of a liquid, crystal display module of a TFT type or the like, the number of steps of gray scales is increasing from 64 to 256 and a voltage step per gray scale (a voltage difference between two successive gray scale voltages) in the plurality of gray scale voltages generated by the multi-gray scale voltage generating circuit becomes small.
An offset voltage is produced in the amplifier circuit by variations in properties of active elements constituting the amplifier circuit and when the offset voltage is produced in the amplifier circuit, an error is caused in an output voltage from the amplifier circuit and the output voltage from the amplifier circuit becomes a voltage different from a specified gray scale.
Thereby, there poses a problem in that black or white vertical lines are generated in a display screen displayed in the liquid crystal display panel (TFT-LCD) and display quality is significantly deteriorated. A liquid crystal display device of a liquid crystal display module of a TFT type or the like has a tendency toward a larger screen size and a higher display resolution (a larger number of pixels) of a liquid crystal display panel (TFT-LCD), and also there is requested a reduction of the border areas such that areas other than a display area of the liquid crystal display panel are made as small as possible in order to eliminate non-useful area and achieve aesthetic qualities as a display device.
Further, the level shift circuit installed at the first stage of the gray scale voltage selector is constituted by transistors having a high voltage breakdown capacity between the source and the drain.
However, when transistors having a high-voltage rating are used as the transistors for the level shift circuit, there poses a problem in that an area of the level shift circuit becomes large in a semiconductor integrated circuit (IC chip) constituting the drain driver, the chip size of the semiconductor integrated circuit constituting the drain driver becomes large, the unit cost of the chip cannot be lowered and the reduction of the border areas cannot be achieved.
Further, conventionally, in a liquid crystal display device, a higher resolution liquid crystal display panel has been requested, the resolution of a liquid crystal display panel has been enlarged from 640×480 pixels of a VGA (Video Graphics Array) display mode to 800×600 pixels of an SVGA (Super VGA) display mode. In recent years, in a liquid crystal display device, in accordance with a request for a larger, screen size of a liquid crystal display panel, as a resolution of a liquid crystal display panel, there has been requested a further higher resolution of 1024×768 pixels of an XGA (Extended Video Graphics Array) display mode, 1280×1024 pixels of an SXGA (Super Extended Video Graphics Array) display mode or 1600×1200 pixels of a UXGA (Ultra Extended Video Graphics Array) display mode.
In accordance with such a higher resolution of a liquid crystal panel, a display control circuit, drain drivers and gate drivers are obliged to carry out high-speed operation, and more particularly, there has been requested high-speed operation for a clock for latching display data (CL2) outputted from the display control circuit to the drain driver and an operating frequency of display data.
Thereby, there poses a problem in that a timing margin is reduced when display data is latched inside of a semiconductor integrated circuit constituting the drain driver.